The present invention relates to two-dimensional imaging. More particularly, the invention relates to a device and method for forming a two-dimensional image sensor array with amorphous TFTs and polysilicon TFTs integrated on the same substrate. The polysilicon TFTs, are constructed to provide multiplexing to the data and gate lines of the image sensor, thereby reducing the number of peripheral contacts and simplifying the packaging of the image sensor.
Addressable two-dimensional image sensor arrays made from amorphous silicon were discussed by M. Matsumura et al (IEEE Electron Device Letters, vol. EDL-1, page 182, 1980) and were demonstrated by Street et al (Material Research Society Symposium Proceedings, vol. 258, page 1127, 1992). Street et al (Material Research Society Symposium Proceedings, vol. 192, page 441, 1990) describe the use of large area amorphous silicon arrays together with a suitable phosphor for x-ray imaging.
An equivalent circuit diagram of a conventional two-dimensional image sensor is depicted in FIG. 1A.
A sensor portion is a structural unit of the image sensor that comprises a substrate 10 having formed thereon a light-receiving element (photodiode) 12 which is a photoelectric transducer and a thin-film transistor (TFT) 14 which is a switching element. A plurality of such sensor portions are arranged in rows and columns in a two-dimensional matrix array to form a sensing area.
FIG. 1B illustrates an equivalent circuit diagram for one pixel of an image sensor according to the subject invention. It is to be appreciated FIG. 1B represents one type of pixel configuration and other arrangements may be used in connection with the subject invention. When light falls on a photodiode (PD) supplied with a reverse bias voltage (V.sub.B), a photocurrent (ip) is generated and supplied to a photodiode capacitance (C.sub.PD), an optional added capacitance (C.sub.ADD), and an overlap capacitance (C.sub.GD) of a thin-film transistor (TFT), where these capacitances are all on the PD side. The charges are stored for a predetermined time in the capacitances on the (PD) side until the TFT is switched on by the gate pulse, whereby those charges are transferred to a signal line capacitance (C.sub.L) and an overlap capacitance (C.sub.GS) of the TFT which are both capacitances on a signal line side.
Data line signals are transferred to external read out amplifiers (see for example 22 of FIG. 1A) and sensed by voltage detection or charge sensitive amplifiers. After detecting the potential (V.sub.L) or charge on the signal line side following the end of charge transfer, resetting of charges are accomplished with a reset switch in order to transfer the charges generated from the PDs in the next row.
One side of the light-receiving element 12 in each sensor portion is connected to a bias line and the other side to the drain of the thin-film transistor 14. The gates of individual thin-film transistors are connected to a common gate line 16 for each row, such gate lines 16 being connected for each row to an external shift register 18 which controls the turning on and off of the thin-film transistors for each row. The source electrodes of the thin-film transistors 14 are connected to a common data line 20 for each column, such data lines 20 in turn are connected to external analog multiplexers or assorted amplifying circuitry 22 for reading out charge from the light receiving element.
In the image sensor having the configuration described above, charges are generated in the light-receiving elements 12 in accordance to the quantity of light or radiation incident on a surface and, as the thin-film transistors 14 are turned on and off, the charges are transferred sequentially into the external analog multiplexers 22 for each row, and are then read to produce output image signals.
In the conventional two-dimensional image sensor described above, the gate lines 16 (which control TFTs for each row) are provided in one-to-one correspondence with the terminals of the external shift registers 18 and, hence, it has been necessary to provide as many terminals on the external shift registers 18 as the gate lines 16. In addition, the charges generated in the sensor portions are to be read into the external analog multiplexers 22 by means of the operation of the common gate lines 16 and, hence, it also has been necessary to provide as many terminals on the external analog multiplexers 22 as the data lines 20. This results in at least n+m contacts along the edges of the image sensor, where n is equal to the number of data lines and m is equal to the number of gate lines.
It has been shown that both amorphous silicon (a-Si) and polycrystalline silicon (poly-Si) are well suited for use in large area electronic applications, such as the abovedescribed two-dimensional image sensor and for flat panel active-matrix displays, etc. Amorphous silicon TFTs are now routinely used as the switching element in commercial products due to their ease and cost of manufacture. Amorphous silicon TFTs possess very low leakage currents, approximately 10.sup.-15 A/.mu.m width at 10 V drain to source bias, and adequate drive currents to charge pixels in high resolution 1000 line imagers.
It is desirable to reduce the number of external connections to these arrays in order to simplify the connection between the external drive and read out electronics. Reduction at the number of external contacts requires integrating higher speed driver electronics on the same substrate as the amorphous silicon TFTs. Laser crystallized a-Si TFTs are suitable for this integration due to their high speed and similarity and process compatibility with the pixel a-Si TFTs. In large two-dimensional arrays only linear arrays of TFTs need to be crystallized to provide the peripheral driver electronics with the remainder of a-Si being maintained for their low leakage characteristics.
Fabrication of both a-Si and poly-Si TFTs on the glass substrate have been reported. Such fabrication includes integration of both poly-Si and a-Si TFTs for top-gate devices and bottom-gate devices. However, top-gate structures are known to be inferior for a-Si TFTs. Therefore, integration of both the poly-Si and a-Si TFTs for bottom-gate devices are deemed more useful. The processes for such integration differ mainly in the inclusion of a laser treatment and a hydrogen passivation step to form the polysilicon TFTs. A detailed discussion regarding this fabrication process is set forth in an article by M. Hack, P. Mei, R. Lujan, and A. G. Lewis, entitled, INTEGRATED CONVENTIONAL AND LASER CRYSTALLIZED AMORPHOUS SILICON THIN-FILM TRANSISTORS FOR LARGE AREA IMAGING AND DISPLAY APPLICATIONS, Journal of Non-Crystalline Solids 164-166 (1993) 727-730 and an article by P. Mei, J. B. Boyce, M. Hack, R. A. Lujan, R. I. Johnson, G. B. Anderson, D. K. Fork, and S. E. Ready, entitled, LASER DEHYDROGENATION/CRYSTALLIZATION OF PLASMAENHANCED CHEMICAL VAPOR DEPOSITED AMORPHOUS SILICON FOR HYBRID THIN-FILM TRANSISTORS, App. Phys. Lett. 64(9), 28 Feb., 1994, both of which are herein incorporated by reference.
An above described image sensor, formed as an N.times.M matrix sensor, implementing polysilicon and amorphous silicon TFTs on a single substrate has the potential for very high speed document input by contact or projection imaging. Further, applications for imaging x-rays and other ionizing radiation are expected. However, such an N.times.M matrix sensor array, in its simplest form still needs a total of n+m contacts along its edges. Therefore, when attempting to construct such a device of a size approximately 14".times.18" or larger, with a resolution of 200 spots per inch (spi), 300 spots per inch (spi), or greater, known packaging technology is severely strained. With known fabrication technology a format of 14".times.18" or larger requires the tiling of at least four (4) individual arrays. Under such an arrangement, the contacts are confined to two sides of the array, thereby requiring a pitch of 127 .mu.m for a 200 spi array and 85 .mu.m for a 300 spi array. This results in a major challenge for wire-bonding, increasing the cost and decreasing the efficiencies of throughput, and cannot yet be done with tape automated bonding (TAB) packaging.
The subject invention overcomes these shortcomings and others as will be set forth below.